Tilera Handles throughput at different frame sizes slightly better than x86 Tilera Not currently limited by ASIC.
x86 More CPU and power is required to move data at the same speed as a CCR x86 Not limited by ASIC, x86 can process multiple tables more quickly than CCR if the HV host has a high clock speed CPU. Throughput At 1500 bytes, 512 bytes and 64 bytes Routing table size Impact of multiple tables x86 Better for heavy computational work. CCR for full BGP tables? Platform CPU BGP routers with full tables have a high computational requirement.
0 kommentar(er)
